The present disclosure relates to integrated circuit design and more particularly to fabricating resistors in semiconductor layers of field effect transistors.
Electronic devices, particularly integrated circuits, comprise a large number of components fabricated by layering several different materials onto a silicon wafer. In order for the components to function as an electronic device, they are selectively, electrically connected to one another. Metal lines are utilized to electrically connect components. The metal lines provide electrical connection within a layer, while vias connect different metallization and via layers.
In modern integrated circuits, a high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like may be formed on a single chip area. Typically, feature sizes of such circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
Although transistor elements are the dominant circuit element in highly complex integrated circuits, which substantially determine the overall performance of these devices, other components, such as capacitors and resistors, may be required. The size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area.